1. Technical Field
The present invention relates to a method of manufacturing a semiconductor device, and a control system.
2. Related Art
In recent semiconductor elements, delay in signal transmission in interconnects determines operation speed of elements. Delay constant of signal transmission in interconnects is expressed by a product of resistivity of interconnects and capacitance between the adjacent interconnects. Therefore, in view of increasing the operation speed of elements, there are growing trends of using low-dielectric-constant materials having dielectric constants smaller than that of conventional silicon oxide (SiO2) film as an insulating interlayer, and of using copper (Cu) having small resistivity as the interconnects.
Multi-layer interconnects using copper as an interconnect material are formed by the damascene process. In the damascene process, recesses such as interconnect trenches and via holes are formed in an insulating interlayer by etching through a resist film having a predetermined pattern formed therein, a barrier metal film is deposited in the recesses, the recesses are filled with a copper film, and portions of the copper film and the barrier metal film extended outside the recesses are removed by chemical mechanical polishing (CMP), to thereby form copper interconnects or copper vias.
In the damascene process, any interconnects designed under the same dimension should have the same resistivity on a semiconductor substrate, in view of controlling operation timing and operation voltage of transistors exactly as they are designed. It is therefore necessary to form the interconnects and the vias exactly as they are designed. Because the interconnects and the vias in the damascene process are formed by filling the recesses with the copper film as described in the above, it is necessary to form the recesses with uniform sectional area for desirable dimensional control. In other words, precise control of width and depth of the recesses is required.
However in multi-layer structure, the individual layers have different aperture ratios of pattern (ratio of areas of interconnects and vias to the total area of a layer, also referred to as data ratio). For example, the upper layer having a large ratio of source interconnects which handle large current tends to have a larger aperture ratio than the lower layer has. Taking difference by product into consideration, the aperture ratio of pattern on the substrate may vary approximately from 20 to 80%.
There has been a problem in that difference in the aperture ratio of pattern resulted in varied width of obtainable recesses, even if mask patterns having the same pattern width was used. In order to form the interconnect patterns exactly as they are designed in the multi-layer structure, it is therefore necessary to establish a manufacturing process not susceptible to dimensional fluctuation even under different aperture ratios of pattern.
There have been known conventional techniques of correcting dimensional changes corresponding to the aperture ratio of the individual layers to be etched.
Japanese Laid-Open Patent Publication No. H9-82691 describes a technique of shortening retention time of an etching gas when the aperture ratio of a layer to be etched is large or when an etching mask has a reversely-tapered profile, and elongating the retention time of the etching gas in the reverse situation. The technique is reportedly successful in reducing critical dimension loss dependent to the aperture ratio of the layer to be etched and taper angle of the etching mask.
Japanese Laid-Open Patent Publication No. H9-326382 describes a technique of carrying out etching after determining etching parameters depending on the area of opening in which the etching proceeds. The document describes a technique of etching a bulk portion of aluminum alloy, while reducing flow rate of chlorine as the area to be etched increases.
Japanese Laid-Open Patent Publication No. 2004-311972 describes etching capable of suppressing the dimensional shift and of obtaining a desired etching profile, irrespective of pattern to be formed, by allowing etching to proceed while using a focus ring having a surface area corresponded to the aperture ratio of pattern of an object to be etched, so as to control amount of fluorine radical to be scavenged.
By the way, with advancement of shrinkage of semiconductor devices, fine processing has been becoming more necessary also for etching technique using photoresist. Three-layer resist process has been known as a method of fine processing. In the three-layer resist process, first, a thick lower resist is coated over a layer on the substrate as a target of fine processing. Next, an intermediate film is formed over the lower resist layer. Further thereon, an upper resist layer, typically a resist film adapted to ArF lithography, is formed by coating, the upper resist layer is subjected to lithographic exposure and development, to thereby form a mask used for processing. If any misalignment should occur, only the upper resist layer is removed by O2 ashing or by stripping using an organic solvent, the upper resist layer is formed again, and subjected to lithographic exposure and development. Japanese Laid-Open Patent Publication No. H7-183194 describes a technique of forming an intermediate film of three-layered resists by high density plasma CVD, aiming at improving critical dimension loss and pattern profile in the process of etching the lower resist layer. As the intermediate film herein, a SiO2 film formed by low-temperature CVD is adopted.
Japanese Laid-Open Patent Publication No. 2006-32908 describes a technique of etching an organic anti-reflective film through a mask layer composed of ArF resist, in which dimension of an opening formed in an anti-reflective film is controlled by varying radio-frequency power applied for raising plasma. The technique is reportedly successful in making dimension of opening of the organic anti-reflective film smaller than dimension of opening pattern of the mask layer before the etching. It is also described that, in such etching of the organic anti-reflective film, changes in the applied radio-frequency power applied for raising plasma may result in CD shift, which is defined as an amount of shift of diameter of opening measured at the bottom of the anti-reflective film (bottom CD) to diameter of opening measured at the top of the mask layer (top CD) in the center portion of a wafer.
However, the technique described in Japanese Laid-Open Patent Publication No. 2004-311972 needs recovery of atmospheric pressure of a process chamber of a vacuum apparatus for detachment and attachment of the focus ring, every time layers of different aperture ratios are processed. It takes a long time to achieve a steady vacuum state of the chamber again from the atmospheric pressure, and this means increase in so-called down time and serious degradation of operational efficiency of the apparatus.
The techniques described in Japanese Laid-Open Patent Publication Nos. H9-82691 and H9-326382 correct dimensional shift corresponded to the aperture ratios of layers to be etched, by varying etching conditions under which the layers to be processed contained in the final products (for example, a refractory metal-containing polycide layer in Japanese Laid-Open Patent Publication No. H9-82691, and a SiO2 film in Japanese Laid-Open Patent Publication No. H9-326382) are etched. However, the present inventors found out from their investigations that, in the process of forming the interconnect trench by the damascene process, it was difficult to correct the dimensional shift under a good controllability, even with every effort of correcting the dimensional shift corresponded to the aperture ratio of pattern, by controlling etching conditions under which the insulating interlayer, as a target for forming the interconnect trench, is etched.
Japanese Laid-Open Patent Publication No. 2006-32908 describes control of the dimension of opening of the anti-reflective film, which resides only in the process of manufacturing but not remains in the final product, but what is important is a dimension of a material contained in the final product, in view of ensuring good electrical characteristics of the final product. The dimension of the material contained in the final product cannot always be controlled to a desired value, even if the dimension of opening of the anti-reflective film might be controlled to a predetermined value. As described later referring to FIG. 19, the dimensional control of the insulating interlayer to be processed, contained in the final product, resulted in failure, even if radio-frequency power (top power) to be applied was varied.